William R. Patterson Senior Lecturer in Engineering

William R. Patterson III is a Senior Lecturer and Senior Research Engineer in the Division of Engineering. His current research focuses on circuit and instrument design for implantable neural sensors and for studies of aggressively scaled CMOS transistors. His work on neural recording from the motor cortex of primates and humans centers on the design of custom integrated circuits to move all electronics for signal capture and processing inside the skull. A multi-amplifier custom integrated circuit mounts on the back of an array of extra-cellular microprobes. Depending on the application, the circuit is powered optically or by RF and data returns by infrared link either over fiber or transcutaneously.

He also collaborates on probabilistic methods to analyze and improve digital circuit design. This work aims to anticipate and solve problems that will occur as industry pushes transistor sizes toward the ultimate limits of CMOS operation.

Brown Affiliations

scholarly work

K. Nepal , R. I. Bahar, J. Mundy, W. R. Patterson, and A. Zaslavsky, Designing MRF based Error Correcting Circuits for Memory Elements, IEEE/ACM Design Automation and Test in Europe Conference, March 2006

William R. Patterson, Yoon-Kyu Song, Christopher W. Bull, Ilker Ozden, Andrew P. Deangelis, Christopher Lay, J. Lucas McKay, Arto V. Nurmikko, John D. Donoghue, and Barry W. Connors, A Microelectrode/Microelectronic Hybrid Device for Brain Implantable Neuroprosthesis Applications, IEEE Transactions on Biomedical Engineering, v51 No. 10 (October 2004) pp. 1845-1853.

H. F. Silverman, W. R. Patterson III, J. M. Sachar, Factors Affecting the Performance of Large-Aperture Microphone Arrays, J. Acoustical Soc. V111 Pt.1, May 2002, pp. 2140-2157

research overview

Mr. Patterson's research focuses on circuit and instrument design for a variety of applications. Most recently those applications include circuits for implantable neural sensors to do chronic recording in the cortex, for studies of the limiting factors in CMOS transistor sizing, and for microphone-array applications.

research statement


funded research

National Science Foundation Grant under Nanotechnology Interdisciplinary Research Teams entitled Fault-tolerant, Probabilistic Computing with Markov Random Field Architectures and CMOS Nanodevices. Principal investigators: R. Iris Bahar, Joseph Mundy, William Patterson, and Alexander Zaslavsky. Award date: September 2005. Award amount: $317,000.