R. Iris Bahar received the B.S. and M.S. degrees in computer engineering from the University of Illinois, Urbana-Champaign, and the Ph.D. degree in electrical and computer engineering from the University of Colorado, Boulder. Before entering the Ph.D program at CU-Boulder, she worked for Digital Equipment Corporation on their VAX microprocessor designs. She has been on the faculty at Brown University since 1996 and now holds a dual appointment as Professor of Engineering and Professor of Computer Science. Her research interests focus on energy-efficient and reliable computing, from the system level to device level. Most recently, this includes applications for near-data processing and hardware/software design of robust machine learning techniques for robot scene perception. She is a recipient of the National Science Foundation CAREER award, the Marie R. Pistilli Women in Engineering Achievement Award and the Brown University School of Engineering Award for Excellence in Teaching in Engineering.
Publications can be found on ORCID:
https://orcid.org/0000-0001-6927-8527
Choe, Jiwon, Moreshet, Tali, Bahar, R. Iris, Herlihy, Maurice. "Attacking memory-hard scrypt with near-data-processing." Proceedings of the International Symposium on Memory Systems - MEMSYS '19, 2019. |
Nepal, Kumud, Hashemi, Soheil, Tann, Hokchhay, Bahar, R. Iris, Reda, Sherief. "Automated High-Level Generation of Low-Power Approximate Computing Circuits." IEEE Transactions on Emerging Topics in Computing, vol. 7, no. 1, 2019, pp. 18-30. |
Choe, Jiwon, Huang, Amy, Moreshet, Tali, Herlihy, Maurice, Bahar, R. Iris. "Concurrent Data Structures with Near-Data-Processing." The 31st ACM on Symposium on Parallelism in Algorithms and Architectures - SPAA '19, 2019. |
X. Chen, R. Chen, Z. Sui, Z. Ye, Y. Liu, R. I. Bahar, O. C. Jenkins. "GRIP: Generative Robust Inference and Perception for Semantic Robot Manipulation in Adversarial Environments." 2019. |
Dimitra Papagiannopoulou, Sungseob Whang, Tali Moreshet, R. Iris Bahar. "IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM." 2019. |
Bahar, R. Iris, Karpuzcu, Ulya, Misailovic, Sasa. "Special Session: Does Approximation Make Testing Harder (or Easier)?." 2019 IEEE 37th VLSI Test Symposium (VTS), 2019. |
Donato, Marco, Bahar, R. Iris, Patterson, William R., Zaslavsky, Alexander. "A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 3, 2018, pp. 643-656. |
Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Luca Benini, Maurice Herlihy, R. Iris Bahar. "Hardware Transactional Memory Exploration in Coherence-free Many-core Architectures." International journal of parallel programming, vol. 46, no. 6, 2018, pp. 1304–1328. |
Y. Liu, Z. Sui, A. Costantini, Z. Ye, S. Lu, O. C. Jenkins, R. I. Bahar. "Robust Object Estimation using Generative-Discriminative Inference for Secure Robotics Applications." Proceedings of, 2018, pp. 8 pages. |
Harris, Christopher B., Bahar, R. Iris. "Towards the Simulation Based Design and Validation of Mobile Robotic Cyber-Physical Systems." Journal of Low Power Electronics, vol. 14, no. 1, 2018, pp. 148-156. |
Harris, Christopher B., Bahar, R. Iris. "A Research Tool for the Power and Performance Analysis of Sensor-Based Mobile Robots." 2017 New Generation of CAS (NGCAS), 2017. |
Christopher Picardo, Justin Delva, R. Iris Bahar. "Comprehensive Comparison of Gradient-Based Cross-Spectral Stereo Matching Generated Disparity Maps." 2017. |
Papagiannopoulou, Dimitra, Marongiu, Andrea, Moreshet, Tali, Herlihy, Maurice, Bahar, R. Iris. "Edge-TM: Exploiting Transactional Memory for Error Tolerance and Energy Efficiency." ACM Transactions on Embedded Computing Systems, vol. 16, no. 5s, 2017, pp. 1-18. |
Whang, Sungseob, Rachford, Tymani, Papagiannopoulou, Dimitra, Moreshet, Tali, Bahar, R. Iris. "Evaluating critical bits in arithmetic operations due to timing violations." 2017 IEEE High Performance Extreme Computing Conference (HPEC), 2017. |
Tann, Hokchhay, Hashemi, Soheil, Bahar, R. Iris, Reda, Sherief. "Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks." Proceedings of the 54th Annual Design Automation Conference 2017 on - DAC '17, 2017. |
Hashemi, Soheil, Anthony, Nicholas, Tann, Hokchhay, Bahar, R. Iris, Reda, Sherief. "Understanding the impact of precision quantization on the accuracy and energy of neural networks." Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017. |
Donato, Marco, Bahar, R. Iris, Patterson, William, Zaslavsky, Alexander. "A fast simulator for the analysis of sub-threshold thermal noise transients." Proceedings of the 53rd Annual Design Automation Conference on - DAC '16, 2016. |
Hashemi, Soheil, Bahar, R. Iris, Reda, Sherief. "A low-power dynamic divider for approximate applications." Proceedings of the 53rd Annual Design Automation Conference on - DAC '16, 2016. |
Han, Xijing, Donato, Marco, Bahar, R. Iris, Zaslavsky, Alexander, Patterson, William. "Design of Error-Resilient Logic Gates with Reinforcement Using Implications." Proceedings of the 26th edition on Great Lakes Symposium on VLSI - GLSVLSI '16, 2016. |
Ulusel, Onur, Picardo, Christopher, Harris, Christopher B., Reda, Sherief, Bahar, R. Iris. "Hardware acceleration of feature detection and description algorithms on low-power embedded platforms." 2016 26th International Conference on Field Programmable Logic and Applications (FPL), 2016. |
Tann, Hokchhay, Hashemi, Soheil, Bahar, R. Iris, Reda, Sherief. "Runtime configurable deep neural networks for energy-accuracy trade-off." Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES '16, 2016. |
Carle, Thomas, Papagiannopoulou, Dimitra, Moreshet, Tali, Marongiu, Andrea, Herlihy, Maurice, Bahar, R. Iris. "Thrifty-malloc: A HW/SW Codesign for the Dynamic Management of Hardware Transactional Memory in Embedded Multicore Systems." Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems - CASES '16, 2016. |
Donato, Marco, Bahar, R. Iris, Patterson, William, Zaslavsky, Alexander. "A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits." Proceedings of the 25th edition on Great Lakes Symposium on VLSI - GLSVLSI '15, 2015. |
Hashemi, Soheil, Bahar, R. Iris, Reda, Sherief. "DRUM: A Dynamic Range Unbiased Multiplier for approximate applications." 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2015. |
Papagiannopoulou, Dimitra, Capodanno, Giuseppe, Moreshet, Tali, Herlihy, Maurice, Bahar, R. Iris. "Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems." ACM Transactions on Embedded Computing Systems, vol. 14, no. 3, 2015, pp. 1-27. |
Papagiannopoulou, Dimitra, Marongiu, Andrea, Moreshet, Tali, Benini, Luca, Herlihy, Maurice, Bahar, Iris. "Playing with Fire: Transactional Memory Revisted for Error-Resilient and Energy-Efficient MPSoC Execution." Proceedings of the 25th edition on Great Lakes Symposium on VLSI - GLSVLSI '15, 2015. |
Nepal, Kundan, Alhelaly, Soha, Dworak, Jennifer, Bahar, R. Iris, Manikas, Theodore, Guikundan, Ping. "Repairing a 3-D Die-Stack Using Available Programmable Logic." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 5, 2015, pp. 849-861. |
Nepal, Kumud, Li, Yueting, Bahar, R. Iris, Reda, Sherief. "ABACUS: A technique for automated behavioral synthesis of approximate computing circuits." Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, 2014. |
Ulusel, Onur, Nepal, Kumud, Bahar, R. Iris, Reda, Sherief. "Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators." ACM Trans. Reconfigurable Technol. Syst., vol. 7, no. 1, 2014, pp. 1-22. |
Papagiannopoulou, Dimitra, Moreshet, Tali, Marongiu, Andrea, Benini, Luca, Herlihy, Maurice, Iris Bahar, R. "Speculative synchronization for coherence-free embedded NUMA architectures." 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), 2014. |
Nepal, Kundan, Shen, Xi, Dworak, Jennifer, Manikas, Theodore, Bahar, R. Iris. "Built-in Self-Repair in a 3D die stack using programmable logic." 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2013. |
Papagiannopoulou, D., Prasertsom, P., Bahar, I. "Flexible data allocation for scratch-pad memories to reduce NBTI effects." International Symposium on Quality Electronic Design (ISQED), 2013. |
Papagiannopoulou, Dimitra, Bahar, R. Iris, Moreshet, Tali, Herlihy, Maurice, Marongiu, Andrea, Benini, Luca. "Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs." Proceedings of the First International Workshop on Many-core Embedded Systems - MES '13, 2013. |
Donato, Marco, Cremona, Fabio, Jin, Warren, Bahar, R. Iris, Patterson, William, Zaslavsky, Alexander, Mundy, Joseph. "A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic." Proceedings of the great lakes symposium on VLSI - GLSVLSI '12, 2012. |
Nepal, Kumud, Ulusel, Onur, Bahar, R. Iris, Reda, Sherief. "Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators." 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, 2012. |
Le, Roto, Mundy, Joseph L., Bahar, R. Iris. "High Performance Parallel JPEG2000 Streaming Decoder Using GPGPU-CPU Heterogeneous System." 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors, 2012. |
Ferri, Cesare, Papagiannopoulou, Dimitra, Bahar, R. Iris, Calimera, Andrea. "NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems." Journal of Electronic Testing, vol. 28, no. 3, 2012, pp. 349-363. |
Jannaty, Pooya, Sabou, Florian C., Le, Son T., Donato, Marco, Bahar, R. Iris, Patterson, William, Mundy, Joseph, Zaslavsky, Alexander. "Shot-Noise-Induced Failure in Nanoscale Flip-Flops Part II: Failure Rates in 10-nm Ultimate CMOS." IEEE Trans. Electron Devices, vol. 59, no. 3, 2012, pp. 807-812. |
Jannaty, Pooya, Sabou, Florian C., Le, Son T., Donato, Marco, Donato, R. Iris, Donato, William, Mundy, Joseph, Zaslavsky, Alexander. "Shot-Noise-Induced Failure in Nanoscale Flip-Flops—Part I: Numerical Framework." IEEE Trans. Electron Devices, vol. 59, no. 3, 2012, pp. 800-806. |
Dworak, Jennifer, Nepal, Kundan, Alves, Nuno, Shi, Yiwen, Imbriglia, Nicholas, Iris Bahar, R. "Using implications to choose tests through suspect fault identification." ACM Trans. Des. Autom. Electron. Syst., vol. 18, no. 1, 2012, pp. 1-19. |
Le, Roto, Bahar, Iris R., Mundy, Joseph L. "A novel parallel Tier-1 coder for JPEG2000 using GPUs." 2011 IEEE 9th Symposium on Application Specific Processors (SASP), 2011. |
Alves, N., Shi, Y., Imbriglia, N., Dworak, J., Nepal, K., Bahar, R.I. "Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis." 2011 Sixteenth IEEE European Test Symposium, 2011. |
Alves, N., Shi, Y., Dworak, J., Bahar, R. I., Nepal, K. "Enhancing online error detection through area-efficient multi-site implications." 29th VLSI Test Symposium, 2011. |
Jannaty, Pooya, Sabou, Florian Cosmin, Bahar, R. Iris, Mundy, Joseph, Patterson, William R., Zaslavsky, Alexander. "Full Two-Dimensional Markov Chain Analysis of Thermal Soft Errors in Subthreshold Nanoscale CMOS Devices." IEEE Transactions on Device and Materials Reliability, vol. 11, no. 1, 2011, pp. 50-59. |
Ferri, Cesare, Papagiannopoulou, Dimitra, Bahar, R. Iris, Calimera, Andrea. "NBTI-aware data allocation strategies for scratchpad memory based embedded systems." 2011 12th Latin American Test Workshop (LATW), 2011. |
Ferri, Cesare, Marongiu, Andrea, Lipton, Benjamin, Bahar, R. Iris, Moreshet, Tali, Benini, Luca, Herlihy, Maurice. "SoC-TM." Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '11, 2011. |
Tadesse, Desta, Bahar, R. Iris, Grodstein, Joel. "Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems." Journal of Electronic Testing, vol. 27, no. 2, 2011, pp. 123-136. |
Alves, Nuno, Buben, Alison, Nepal, Kundan, Dworak, Jennifer, Bahar, R. Iris. "A Cost Effective Approach for Online Error Detection Using Invariant Relationships." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 5, 2010, pp. 788-801. |
Calimera, A., Bahar, R.I., Macii, E., Poncino, M. "Dual- assignment policies in ITD-aware synthesis." Microelectronics Journal, vol. 41, no. 9, 2010, pp. 547-553. |
Ferri, Cesare, Wood, Samantha, Moreshet, Tali, Iris Bahar, R., Herlihy, Maurice. "Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems." Journal of Parallel and Distributed Computing, vol. 70, no. 10, 2010, pp. 1042-1052. |
Ferri, Cesare, Wood, Samantha, Moreshet, Tali, Bahar, Iris, Herlihy, Maurice. "Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems." Automata, Languages and Programming, 2010, pp. 50-65. |
Alves, Nuno, Nepal, Kundan, Dworak, Jennifer, Bahar, R. Iris. "Improving the testability and reliability of sequential circuits with invariant logic." Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10, 2010. |
Jannaty, Pooya, Sabou, Florian C., Bahar, R. Iris, Mundy, Joseph, Patterson, William R., Zaslavsky, Alexander. "Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices." Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10, 2010. |
Calimera, Andrea, Bahar, R. Iris, Macii, Enrico, Poncino, Massimo. "Temperature-Insensitive Dual-Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 11, 2010, pp. 1608-1620. |
Jannaty, Pooya, Sabou, Florian C., Gadlage, Matthew, Bahar, R. Iris, Mundy, Joseph, Patterson, William, Reed, Robert A., Weller, Robert A., Schrimpf, Ronald D., Zaslavsky, Alexander. "Two-Dimensional Markov Chain Analysis of Radiation-Induced Soft Errors in Subthreshold Nanoscale CMOS Devices." IEEE Trans. Nucl. Sci., 2010. |
Tadesse, D., Grodstein, J., Bahar, R. I. "AutoRex: An automated post-silicon clock tuning tool." 2009 International Test Conference, 2009. |
Alves, Nuno, Dworak, Jennifer, Bahar, Iris, Nepal, K. "Compacting test vector sets via strategic use of implications." Proceedings of the 2009 International Conference on Computer-Aided Design - ICCAD '09, 2009. |
Alves, N., Nepal, K., Dworak, J., Bahar, R.I. "Detecting errors using multi-cycle invariance information." 2009 Design, Automation & Test in Europe Conference & Exhibition, 2009. |
Ferri, Cesare, Bahar, Ruth Iris, Loghi, Mirko, Poncino, Massimo. "Energy-optimal synchronization primitives for single-chip multi-processors." Proceedings of the 19th ACM Great Lakes symposium on VLSI - GLSVLSI '09, 2009. |
Le, Roto, Reda, Sherief, Bahar, R. Iris. "High-performance, cost-effective heterogeneous 3D FPGA architectures." Proceedings of the 19th ACM Great Lakes symposium on VLSI - GLSVLSI '09, 2009. |
Bahar, R. Iris. "Introduction to special section." JETC, vol. 5, no. 2, 2009, pp. 1-1. |
Sabou, F.C., Kazazis, D., Bahar, R.I., Mundy, J., Patterson, W.R., Zaslavsky, A. "Markov Chain Analysis of Thermally Induced Soft Errors in Subthreshold Nanoscale CMOS Circuits." IEEE Transactions on Device and Materials Reliability, vol. 9, no. 3, 2009, pp. 494-504. |
Reda, Sherief, Si, Aung, Bahar, R. Iris. "Reducing the leakage and timing variability of 2D ICcs using 3D ICs." Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design - ISLPED '09, 2009. |
Ferri, Cesare, Viescas, Amber, Moreshet, Tali, Bahar, R. Iris, Herlihy, Maurice. "Energy efficient synchronization techniques for embedded architectures." Proceedings of the 18th ACM Great Lakes symposium on VLSI - GLSVLSI '08, 2008. |
Calimera, A., Bahar, R. I., Macii, E., Poncino, M. "Ensuring temperature-insensitivity of dual-Vt designs through ITD-aware synthesis." 2008 14th International Workshop on Thermal Inveatigation of ICs and Systems, 2008. |
Tadesse, Desta, Bahar, Iris, Grodstein, Joel. "Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation." 26th IEEE VLSI Test Symposium (vts 2008), 2008. |
Ferri, Cesare, Reda, Sherief, Bahar, R. Iris. "Parametric yield management for 3D ICs." JETC, vol. 4, no. 4, 2008, pp. 1-22. |
Calimera, Andrea, Bahar, R. Iris, Macii, Enrico, Poncino, Massimo. "Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits." Proceeding of the thirteenth international symposium on Low power electronics and design - ISLPED '08, 2008. |
Calimera, Andrea, Macii, Enrico, Poncino, Massimo, Bahar, R. Iris. "Temperature-insensitive synthesis using multi-vt libraries." Proceedings of the 18th ACM Great Lakes symposium on VLSI - GLSVLSI '08, 2008. |
Calimera, A., Duraisami, K., Sathanur, A., Sithambaram, P., Bahar, R. I., Macii, A., Macii, E., Poncino, M. "Thermal-Aware Design Techniques for Nanometer CMOS Circuits." Journal of Low Power Electronics, vol. 4, no. 3, 2008, pp. 374-384. |
Nepal, K., Alves, N., Dworak, J., Bahar, R.I. "Using Implications for Online Error Detection." 2008 IEEE International Test Conference, 2008. |
Ferri, Cesare, Moreshet, Tali, Bahar, R. Iris, Benini, Luca, Herlihy, Maurice. "A hardware/software framework for supporting transactional memory in a MPSoC environment." ACM SIGARCH Computer Architecture News, vol. 35, no. 1, 2007, pp. 47. |
Tadesse, D., Sheffield, D., Lenge, E., Bahar, R.I., Grodstein, J. "Accurate Timing Analysis using SAT and Pattern-Dependent Delay Models." 2007 Design, Automation & Test in Europe Conference & Exhibition, 2007. |
Bahar, R.I., Lau, C., Hammerstrom, D., Marculescu, D., Harlow, J., Orailoglu, A., Joyner, W.H., Pedram, M. "Architectures for silicon nanoelectronics and beyond." Computer, vol. 40, no. 1, 2007, pp. 25-33. |
Nepal, K., Bahar, R. I., Mundy, J., Patterson, W. R., Zaslavsky, A. "Designing Nanoscale Logic Circuits Based on Markov Random Fields." Journal of Electronic Testing, vol. 23, no. 2-3, 2007, pp. 255-266. |
Ferri, Cesare, Sherief Reda, None, R. Iris Bahar, None. "Strategies for improving the parametric yield and profits of 3D ICs." 2007 IEEE/ACM International Conference on Computer-Aided Design, 2007. |
Nepal, K., Bahar, R. I., Mundy, J., Patterson, W. R., Zaslavsky, A. "Techniques for Designing Noise-Tolerant Multi-Level Combinational Circuits." 2007 Design, Automation & Test in Europe Conference & Exhibition, 2007. |
Li, H., Mundy, J., Patterson, W., Kazazis, D., Zaslavsky, A., Bahar, R. I. "Thermally-induced soft errors in nanoscale CMOS circuits." 2007 IEEE International Symposium on Nanoscale Architectures, 2007. |
Stojanovic, V., Iris Bahar, R., Dworak, J., Weiss, R. "A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors." 2006 43rd ACM/IEEE Design Automation Conference, 2006. |
Nepal, K., Bahar, R.I., Mundy, J., Patterson, W.R., Zaslavsky, A. "Designing MRF based Error Correcting Circuits for Memory Elements." Proceedings of the Design Automation & Test in Europe Conference, 2006. |
Moreshet, Tali, Bahar, R. Iris, Herlihy, Maurice. "Energy implications of multiprocessor synchronization." Proceedings of the eighteenth annual ACM symposium on Parallelism in algorithms and architectures - SPAA '06, 2006. |
Nepal, K., Bahar, R.I., Mundy, J., Patterson, W.R., Zaslavsky, A. "MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits." IEEE Micro, vol. 26, no. 5, 2006, pp. 19-27. |
Nepal, K., Bahar, R. I., Mundy, J., Patterson, W. R., Zaslavsky, A. "Optimizing noise-immune nanoscale circuits using principles of Markov random fields." Proceedings of the 16th ACM Great Lakes symposium on VLSI - GLSVLSI '06, 2006. |
Hui-Yuan Song, None, Nepal, K., Bahar, R.I., Grodstein, J. "Timing analysis for full-custom circuits using symbolic DC formulations." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 9, 2006, pp. 1815-1830. |
Bahar, R. Iris. "Trends and Future Directions in Nano Structure Based Computing and Fabrication." 2006 International Conference on Computer Design, 2006. |
Nepal, K., Bahar, R.I., Mundy, J., Patterson, W.R., Zaslavsky, A. "Designing logic circuits for probabilistic computation in the presence of noise." Proceedings. 42nd Design Automation Conference, 2005., 2005. |
Moreshet, Tali, Bahar, R. Iris, Herlihy, Maurice. "Energy reduction in multiprocessor systems using transactional memory." Proceedings of the 2005 international symposium on Low power electronics and design - ISLPED '05, 2005. |
Bahar, R.I., Hui-Yuan Song, None, Nepal, K., Grodstein, J. "Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 4, 2005, pp. 502-515. |
Bai, Yu, Bahar, R. Iris. "A low-power in-order/out-of-order issue queue." ACM Trans. Archit. Code Optim., vol. 1, no. 2, 2004, pp. 152-179. |
Moreshet, T., Bahar, R.I. "Effects of speculation on performance and issue queue design." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 10, 2004, pp. 1123-1126. |
Mehta, N., Singer, B., Bahar, R.I., Leuchtenburg, M., Weiss, R. "Fetch halting on critical load misses." IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings., 2004. |
Yu Bai, None, Bahar, R.I. "Reducing issue queue power for multimedia applications using a feedback control algorithm." IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings., 2004. |
Nepal, Kundan, Song, Hui-Yuan, Bahar, R. Iris, Grodstein, Joel. "RESTA." Proceedins of the 14th ACM Great Lakes symposium on VLSI - GLSVLSI '04, 2004. |
Yu Bai, None, Bahar, R.I. "A dynamically reconfigurable mixed in-order/out-of-order issue queue for power-aware microprocessors." IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings., 2003. |
Moreshet, Tali, Bahar, R. Iris. "Power-aware issue queue design for speculative instructions." Proceedings of the 40th conference on Design automation - DAC '03, 2003. |
Song, H.-Y., Bohidar, S., Bahar, R.I., Grodstein, J. "Symbolic failure analysis of custom circuits due to excessive leakage current." Proceedings 21st International Conference on Computer Design, 2003. |
Bahar, R. Iris, Manne, Srilatha. "Power and energy reduction via pipeline balancing." Proceedings of the 28th annual international symposium on Computer architecture - ISCA '01, 2001. |
Bahar, R. Iris, Lampe, Ernest T., Macii, Enrico. "Power optimization of technology-dependent circuits based on symbolic computation of logic implications." ACM Trans. Des. Autom. Electron. Syst., vol. 5, no. 3, 2000, pp. 267-293. |
Bahar, R.I., Hyunwoo Cho, None, Hachtel, G.D., Macii, E., Somenzi, F. "Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 10, 1997, pp. 1101-1115. |
Bahar, R.I., Frohm, E.A., Gaona, C.M., Hachtel, G.D., Macii, E., Pardo, A., Somenzi, F. "Algebraic decision diagrams and their applications." Proceedings of 1993 International Conference on Computer Aided Design (ICCAD), 1993. |
Badeau, R.W., Bahar, R.I., Bernstein, D., Biro, L.L., Bowhill, W.J., Brown, J.F., Case, M.A., Castelino, R.W., Cooper, E.M., Delaney, M.A., Deverell, D.R., Edmonson, J.H., Ellis, J.J., Fischer, T.C., Fox, T.F., Gowan, M.K., Gronowski, P.E., Herrick, W.V., Jain, A.K., Meyer, J.E., Miner, D.G., Partovi, H., Peng, V., Preston, R.P., Somanathan, C., Stamm, R.L., Thierauf, S.C., Uhler, G.M., Wade, N.D., Wheeler, W.R. "A 100-MHz macropipelined VAX microprocessor." IEEE J. Solid-State Circuits, vol. 27, no. 11, 1992, pp. 1585-1598. |
Iris Bahar's research interests lie broadly in the areas of computer architecture, electronic design automation, and digital circuit design. In particular, she is working on developing new approaches to reduce power dissipation and improve reliability in high-performance processors, including embedded multiprocessors and nanocomputing systems. In addition, she is working on methods to improve the accuracy of timing analyzers used for verifying circuits designs. Her recent interests have led her to consider robotic system design, and how these systems can benefit from energy-efficient design techniques.
More information about her research be found in her personal home page.
The following is a summary of some of Dr. Bahar's reserch projects:
Because many embedded devices run on batteries, energy efficiency is perhaps the single most important criterion for evaluating hardware and software effectiveness in embedded devices. In this project, we have looked into developing energy-efficient implementations using hardware transactional memory (HTM) on an embedded platform. We also explored implementing more effective memory allocation methods that may be used on top of HTM. A new and ongoing aspect of this work includes exploring how the HTM framework can be used to support error recovery and approximate results caused by aggressive use of voltage over-scaling. This work has been supported by NSF.
A Near-Data Processing (NDP) architecture consists of one or more simple processors each with its own memory. NDP modules are best viewed as accelerators, providing powerful yet specialized enhancements to existing systems running existing software. This project has the dual aim of adapting highly concurrent data structures to NDP architectures, and of adapting NDP architectures to the needs of today’s concurrent software. It also considers how to design durable data structures within the framework of mixed volatile/non-volatile memories. This work is supported by NSF and the US-Israel Binational Science Foundation (BSF).
Electrical noise will play an increasingly critical role in future nanoscale CMOS circuit operation characterized by lower supply voltages and smaller device sizes. Both of these downscaling approaches reduce the margin of immunity to thermal noise, alpha particle strikes, and threshold voltage variations. This project focuses on developing new modeling techniques to capture transient noise effects due to thermal and RTS noise. In addition, we are exploring new approaches for noise-immune circuit design. This work is supported by NSF.
The goal of this project is to implement new algorithms in hardware and software to support accurate and energy-efficient robot perception. In particular, perception is a critical capability to enable purposeful goal-directed manipulation for autonomous robots. Object detection and recognition techniques used for robot perception have greatly improved over the past few years. However, these improvements have often come at the expense of significant energy consumption and computational inefficiency. In order to achieve real-time energy-efficient computing for these autonomous robots, we need to rethink not just the perception algorithms themselves, but also how they are implemented in hardware and the computational resources allocated to their execution.
The goal of this project is to implement new algorithms in hardware and software to support accurate and energy-efficient robot perception. In particular, perception is a critical capability to enable purposeful goal-directed manipulation for autonomous robots. Object detection and recognition techniques used for robot perception have greatly improved over the past few years. However, these improvements have often come at the expense of significant energy consumption and computational inefficiency. In order to achieve real-time energy-efficient computing for these autonomous robots, we need to rethink not just the perception algorithms themselves, but also how they are implemented in hardware and the computational resources allocated to their execution. Initial funding for this work was provided through a Brown SEED grant.
Three-dimensional stacked integrated circuits (ICs) hold much promise for increasing system performance. However, they are also difficult to test and assemble, leading to yield issues. This project investigates the use of unused (or underused) resources within the 3D stack to replace defective portions of a die. In particular, we are exploring techniques for error detection, different levels of granularity for replacement, and optimal use of reconfigurable logic to repair the errors. This work has been supported by NSF.
Current Grants:
Selected Completed Grants:
See list of selected publications.
Year | Degree | Institution |
---|---|---|
1995 | PhD | University of Colorado at Boulder |
1987 | MS | University of Illinois at Urbana-Champaign |
1986 | BS | University of Illinois at Urbana-Champaign |
Name | Title |
---|---|
Herlihy, Maurice | Professor of Computer Science |
Jenkins, Odest | Associate Professor of Computer Science, Associate Professor of Engineering |
Kellner, James | Associate Professor of Ecology and Evolutionary Biology and Environment and Society, Director of Ecology and Evolutionary Biology |
Mundy, Joseph | Professor of Engineering (Research) |
Patterson, William | Distinguished Senior Lecturer in Engineering |
Sloman, Steven | Professor of Cognitive, Linguistic and Psychological Sciences |
Zaslavsky, Alexander | Professor of Engineering, Professor of Physics |
CSCI 2952J - Topics in Computing with Emerging Technologies |
EMSL 2700 - Data Analytics and Machine Learning for Digital Enterprises |
ENGN 1630 - Digital Electronics Systems Design |
ENGN 1931I - Design of Robotic Systems |
ENGN 2912E - Low Power VLSI System Design |