Iris Bahar's research interests lie broadly in the areas of computer architecture, electronic design automation, and digital circuit design. In particular, she is working on developing new approaches to reduce power dissipation and improve reliability in high-performance processors, including embedded multiprocessors and nanocomputing systems. In addition, she is working on methods to improve the accuracy of timing analyzers used for verifying circuits designs.  Her recent interests have led her to consider robotic system design, and how these systems can benefit from energy-efficient design techniques.  

More information about her research be found in her personal home page.

The following is a summary of some of Dr. Bahar's reserch projects:

• Energy Efficient Transactional Memory Techniques for Embedded Architectures

Because many embedded devices run on batteries, energy efficiency is perhaps the single most important criterion for evaluating hardware and software effectiveness in embedded devices. In this project, we have looked into developing energy-efficient implementations using hardware transactional memory (HTM) on an embedded platform.  We also explored implementing more effective memory allocation methods that may be used on top of HTM.  A new and ongoing aspect of this work includes exploring how the HTM framework can be used to support error recovery and approximate results caused by aggressive use of voltage over-scaling.   This work has been supported by NSF.

 

• Concurrent Data Structures using Near-Data-Processing and Non-volatile Memory

A Near-Data Processing (NDP) architecture consists of one or more simple processors each with its own memory.  NDP modules are best viewed as accelerators, providing powerful yet specialized enhancements to existing systems running existing software.  This project has the dual aim of adapting highly concurrent data structures to NDP architectures, and of adapting NDP architectures to the needs of today’s concurrent software.  It also considers how to design durable data structures within the framework of mixed volatile/non-volatile memories.  This work is supported by NSF and the US-Israel Binational Science Foundation (BSF).

 

• Modeling Thermal Noise Effects in Nanoscale Circuits and Designing Noise Tolerant Circuits

Electrical noise will play an increasingly critical role in future nanoscale CMOS circuit operation characterized by lower supply voltages and smaller device sizes. Both of these downscaling approaches reduce the margin of immunity to thermal noise, alpha particle strikes, and threshold voltage variations. This project focuses on developing new modeling techniques to capture transient noise effects due to thermal and RTS noise.  In addition, we are exploring new approaches for noise-immune circuit design. This work is supported by NSF.    

 

• Robust Robot Perception 

The goal of this project is to implement new algorithms in hardware and software to support accurate and energy-efficient robot perception.  In particular, perception is a critical capability to enable purposeful goal-directed manipulation for autonomous robots.  Object detection and recognition techniques used for robot perception have greatly improved over the past few years.  However, these improvements have often come at the expense of significant energy consumption and computational inefficiency.  In order to achieve real-time energy-efficient computing for these autonomous robots, we need to rethink not just the perception algorithms themselves, but also how they are implemented in hardware and the computational resources allocated to their execution.

 

• Building Design Exploration and Analysis Tool for Vision-based Robotic Systems

The goal of this project is to implement new algorithms in hardware and software to support accurate and energy-efficient robot perception.  In particular, perception is a critical capability to enable purposeful goal-directed manipulation for autonomous robots.  Object detection and recognition techniques used for robot perception have greatly improved over the past few years.  However, these improvements have often come at the expense of significant energy consumption and computational inefficiency.  In order to achieve real-time energy-efficient computing for these autonomous robots, we need to rethink not just the perception algorithms themselves, but also how they are implemented in hardware and the computational resources allocated to their execution.  Initial funding for this work was provided through a Brown SEED grant.  

 

• Techniques for Built-in Self-Repair in 3D Die Stacks Using Programmable Logic

Three-dimensional stacked integrated circuits (ICs) hold much promise for increasing system performance.  However, they are also difficult to test and assemble, leading to yield issues.  This project investigates the use of unused (or underused) resources within the 3D stack to replace defective portions of a die.  In particular, we are exploring techniques for error detection, different levels of granularity for replacement, and optimal use of reconfigurable logic to repair the errors.  This work has been supported by NSF.

Current Grants:

• NSF grant: “Effects of Small-scale Noise in Ultimate CMOS:  Simulation Frameworks, Noise-Immune Circuit Designs, and Experimental Validation,” Principal investigators:  R. I. Bahar (PI), A. Zaslavsky, and W. R. Patterson.  Amount:  $360,000, over 3 years.
• NSF grant entitled “Hardware/Software Design of Durable Data Structures and Algorithms for Non-Volatile Main Memory,” Principal investigators:  R. I. Bahar (PI), M. Herlihy, T. Moreshet.  Total amount:  $500,000 over 3 years.
• Brown Seed:  Smarter AI: Designing Autonomous Systems that Optimize Hardware, Software and Cognitive Components Together:  $76K over 18 months. 

 

Selected Completed Grants:

• Brown Seed grant “Enabling Autonomous Flight of Drones in Complex, Unpredictable Environments,” Principal investigators: R. I. Bahar (PI), S. Reda, J. Kellner, O. C. Jenkins.  Total amount:  $80,000 over 12 months. 
• NSF grant entitled “Collaborative Research:  Transparent and Energy-Efficient Speculation on NUMA Architectures for Embedded Multiprocessor Systems,” Principal investigators:  R. I. Bahar (PI) and T. Moreshet (Swarthmore).  Award amount:  $500,000, over 3 years. 
• NSF grant entitled “Automatic High-Level Synthesis of Approximate Computing Circuits,” Principal investigators:  S. Reda (PI) and R. I. Bahar. Total amount:  $449,998 over 3 years. 
• DTRA/ONR grant entitled "Design Science for Radiation-Effects Rate Prediction and Development of Error-Immune Circuitry," Principal investigators: R. I. Bahar (PI), A. Zaslavsky, J. Mundy, and W. Patterson, R. Schrimpf, R. Weller, R. Reed, M. Alles, B. Bhuva. Award date: March 2010. Award amount: $1,400,000
• ARO/ONR/AFOSR equipment grant entitled "DURIP: An Infrared System for Thermal-Driven Research in Computer Vision" Principal investigators: S. Reda, R. I. Bahar, and J. Mundy. Award date: March 2009. Award amount: $126,590.
• NSF/SRC grant entitled "Collaborative Research: Energy-Aware Memory Synchronization for Embedded Mulicore Systems", Principal investigators: R. I. Bahar (PI), M. Herlihy (co-PI), and T. Moreshet (co-PI, Swarthmore College). Award date: August 2009. Award amount: $376,643.
• NSF grant entitled "SHF: Small: Collaborative Research: Using Identified Circuit Invariance for Online Error Detection", Principal investigators: J. Dworak (PI), R. I. Bahar (co-PI), and K. Nepal (co-PI, Bucknell University). Award date: August 2009. Award amount: $476,813.
• DARPA subcontract grant entitled "Wide Area Video Motion Blur Elimination" Principal investigators: R. I. Bahar (PI), J. Mundy and S. Reda. Award date: March 2010. Award amount: $180,000
• National Science Foundation Grant under Nanotechnology Interdisciplinary Research Teams (NIRT) entitled "NIRT: Fault-tolerant, Probabilistic Computing with Markov Random Field Architectures and CMOS Nanodevices" Principal investigators: R. I. Bahar, J. Mundy, W. Patterson, and A. Zaslavsky. Award date: September 2005. Award amount: $317,000.
• Intel Corporation grant entitled "Fast, Accurate Symbolic Timing Analysis for Custom Circuits." Principal investigator, R. Iris Bahar. Award date: October 2005. Award amount: $75,000.
• NSF Grant in the area of Nanotechnology Exploratory Research entitled "NER: Y-Junction Nanotube-based Computer Devices and Architectures" Principal investigators, R. Iris Bahar, Jie Chen and Joseph Mundy. Award date: July 2003. Award amount: $100,000.
• NSF Grant in the area of Design Automation entitled "Using Symbolic DC Analysis to Evaluate Complex Custom Circuit Designs." Principal investigator, R. I. Bahar. Award date: July 2002. Award amount: $160,000.
• NSF Grant in the area of Computer Systems Architecture entitled "Combining Hardware and Software Monitoring for Improved Power and Performance Tuning" Principal investigators, R. I. Bahar and R. Weiss. Award date: August 2003. Award amount: $160,000.
• NSF Grant under Nanotechnology Exploratory Research entitled "NER: Exploring Nanodevices for Probabilistic Computing Architectures." Principal investigators: Alexander Zaslavsky, R. Iris Bahar, Jie Chen and Joseph Mundy. Award date: August 2004. Award amount: $100,000.
• NSF Early Career Development Grant (CAREER) proposal entitled "(Re)Configurable Architectures for High Performance and Low Power." Principal investigator, R. I. Bahar. 6/98–5/03. Award amount: $214,000.
• NSF Professional Opportunities for Women in Research and Education (POWRE) award entitled "Integration of Non-Conventional CMOS Structures into Fully-Automated Synthesis Tools." Principal investigator, R. I. Bahar. 9/98–5/00. Award amount: $75,000.
• Design Automation Graduate Scholarship entitled "Using Implications to Drive Low-Power Optimization of Technology-Dependent Circuits," sponsored by the Design Automation Conference. 9/97–5/98. Award amount: $12,000.
• Richard B. Salomon Faculty Research Award for project entitled "Low-Power VLSI: Designs for the Future." 9/97–5/98. Award amount: $14,500.
• Microsoft Grant for Teaching and Research. The goal of this grant was to become familiar with Windows-based real-time operating systems by using it for operating a life-like robotic head for speech recognition experiments. Principal investigators, R. I. Bahar and H. Silverman. Award date: June 2003. Award amount: $25,000

See list of selected publications.

• IEEE Undergraduate Teaching Award, 2024
• University of Illinois ECE Distinguished Alumni Award, 2022
• IEEE Fellow, 2022
• Marie R. Pistilli Women in Engineering Achievement Award, 2019
• School of Engineering Award for Excellence in Teaching in Engineering, 2019
• IEEE Council on Electronic Design Automation Outstanding Service Award, 2019
• President’s Award for Excellence in Faculty Governance Award, 2018
• ACM Recognition of Service award, 2018
• Distinguished Scientist Award from the Association of Computing Machinery (ACM), 2012
• Awarded Senior Membership to the IEEE, 2012
• NSF Early Career Development (CAREER) Award, 1998.
• Patricia Robert Harris Fellowship to support graduate studies, 1992–1995.
• Eta Kappa Nu, Electrical Engineering Honor Society, since 1985.
• Tau Beta Pi, Engineering Honor Society, since 1985.

Institute of Electrical and Electronic Engineers (IEEE), Senior member

Association of Computing Machinery (ACM), Distinguished Scientist

Professor Bahar's teaching interests include courses on computer architecture, integrated circuit design, electronic design automation, and nanocomputing (or how to effectively design computing systems using various emerging nanotechnologies). She has also been involved in teaching the introductory engineering course at Brown.