### selected

- Donato, Marco, Bahar, R. Iris, Patterson, William, Zaslavsky, Alexander. A fast simulator for the analysis of sub-threshold thermal noise transients Proceedings of the 53rd Annual Design Automation Conference on - DAC '16. 2016 . full text
- Hashemi, Soheil, Bahar, R. Iris, Reda, Sherief. A low-power dynamic divider for approximate applications Proceedings of the 53rd Annual Design Automation Conference on - DAC '16. 2016 . full text
- Nepal, Kumud, Hashemi, Soheil, Tann, Hokchhay, Bahar, R. Iris, Reda, Sherief. Automated High-Level Generation of Low-Power Approximate Computing Circuits IEEE Transactions on Emerging Topics in Computing. 2016 : 1-1 . full text
- Han, Xijing, Donato, Marco, Bahar, R. Iris, Zaslavsky, Alexander, Patterson, William. Design of Error-Resilient Logic Gates with Reinforcement Using Implications Proceedings of the 26th edition on Great Lakes Symposium on VLSI - GLSVLSI '16. 2016 . full text
- Ulusel, Onur, Picardo, Christopher, Harris, Christopher B., Reda, Sherief, Bahar, R. Iris. Hardware acceleration of feature detection and description algorithms on low-power embedded platforms 2016 26th International Conference on Field Programmable Logic and Applications (FPL). 2016 . full text
- Tann, Hokchhay, Hashemi, Soheil, Bahar, R. Iris, Reda, Sherief. Runtime configurable deep neural networks for energy-accuracy trade-off Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES '16. 2016 . full text
- Carle, Thomas, Papagiannopoulou, Dimitra, Moreshet, Tali, Marongiu, Andrea, Herlihy, Maurice, Bahar, R. Iris. Thrifty-malloc: A HW/SW Codesign for the Dynamic Management of Hardware Transactional Memory in Embedded Multicore Systems Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems - CASES '16. 2016 . full text
- Donato, Marco, Bahar, R. Iris, Patterson, William, Zaslavsky, Alexander. A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits Proceedings of the 25th edition on Great Lakes Symposium on VLSI - GLSVLSI '15. 2015 . full text
- Hashemi, Soheil, Bahar, R. Iris, Reda, Sherief. DRUM: A Dynamic Range Unbiased Multiplier for approximate applications 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 2015 . full text
- Papagiannopoulou, Dimitra, Capodanno, Giuseppe, Moreshet, Tali, Herlihy, Maurice, Bahar, R. Iris. Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems TECS. 2015; 14 (3) : 1-27 . full text
- Papagiannopoulou, Dimitra, Marongiu, Andrea, Moreshet, Tali, Benini, Luca, Herlihy, Maurice, Bahar, Iris. Playing with Fire: Transactional Memory Revisted for Error-Resilient and Energy-Efficient MPSoC Execution Proceedings of the 25th edition on Great Lakes Symposium on VLSI - GLSVLSI '15. 2015 . full text
- Nepal, Kundan, Alhelaly, Soha, Dworak, Jennifer, Bahar, R. Iris, Manikas, Theodore, Gui, Ping. Repairing a 3-D Die-Stack Using Available Programmable Logic IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.. 2015; 34 (5) : 849-861 . full text
- Nepal, Kumud, Li, Yueting, Bahar, R. Iris, Reda, Sherief. ABACUS: A technique for automated behavioral synthesis of approximate computing circuits Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014. 2014 . full text
- Ulusel, Onur, Nepal, Kumud, Bahar, R. Iris, Reda, Sherief. Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators TRETS. 2014; 7 (1) : 1-22 . full text
- Papagiannopoulou, Dimitra, Moreshet, Tali, Marongiu, Andrea, Benini, Luca, Herlihy, Maurice, Iris Bahar, R. Speculative synchronization for coherence-free embedded NUMA architectures 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV). 2014 . full text
- Nepal, Kundan, Shen, Xi, Dworak, Jennifer, Manikas, Theodore, Bahar, R. Iris. Built-in Self-Repair in a 3D die stack using programmable logic 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS). 2013 . full text
- Papagiannopoulou, D., Prasertsom, P., Bahar, I. Flexible data allocation for scratch-pad memories to reduce NBTI effects International Symposium on Quality Electronic Design (ISQED). 2013 . full text
- Papagiannopoulou, Dimitra, Bahar, R. Iris, Moreshet, Tali, Herlihy, Maurice, Marongiu, Andrea, Benini, Luca. Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs Proceedings of the First International Workshop on Many-core Embedded Systems - MES '13. 2013 . full text
- Donato, Marco, Cremona, Fabio, Jin, Warren, Bahar, R. Iris, Patterson, William, Zaslavsky, Alexander, Mundy, Joseph. A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic Proceedings of the great lakes symposium on VLSI - GLSVLSI '12. 2012 . full text
- Nepal, Kumud, Ulusel, Onur, Bahar, R. Iris, Reda, Sherief. Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines. 2012 . full text
- Le, Roto, Mundy, Joseph L., Bahar, R. Iris. High Performance Parallel JPEG2000 Streaming Decoder Using GPGPU-CPU Heterogeneous System 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors. 2012 . full text
- Ferri, Cesare, Papagiannopoulou, Dimitra, Bahar, R. Iris, Calimera, Andrea. NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems Journal of Electronic Testing. 2012; 28 (3) : 349-363 . full text
- Jannaty, Pooya, Sabou, Florian C., Le, Son T., Donato, Marco, Bahar, R. Iris, Patterson, William, Mundy, Joseph, Zaslavsky, Alexander. Shot-Noise-Induced Failure in Nanoscale Flip-Flops Part II: Failure Rates in 10-nm Ultimate CMOS IEEE Trans. Electron Devices. 2012; 59 (3) : 807-812 . full text
- Jannaty, Pooya, Sabou, Florian C., Le, Son T., Donato, Marco, Donato, R. Iris, Donato, William, Mundy, Joseph, Zaslavsky, Alexander. Shot-Noise-Induced Failure in Nanoscale Flip-Flops—Part I: Numerical Framework IEEE Trans. Electron Devices. 2012; 59 (3) : 800-806 . full text
- Dworak, Jennifer, Nepal, Kundan, Alves, Nuno, Shi, Yiwen, Imbriglia, Nicholas, Iris Bahar, R. Using implications to choose tests through suspect fault identification ACM Trans. Des. Autom. Electron. Syst.. 2012; 18 (1) : 1-19 . full text
- Le, Roto, Bahar, Iris R., Mundy, Joseph L. A novel parallel Tier-1 coder for JPEG2000 using GPUs 2011 IEEE 9th Symposium on Application Specific Processors (SASP). 2011 . full text
- Alves, N., Shi, Y., Imbriglia, N., Dworak, J., Nepal, K., Bahar, R.I. Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis 2011 Sixteenth IEEE European Test Symposium. 2011 . full text
- Alves, N., Shi, Y., Dworak, J., Bahar, R. I., Nepal, K. Enhancing online error detection through area-efficient multi-site implications 29th VLSI Test Symposium. 2011 . full text
- Jannaty, Pooya, Sabou, Florian Cosmin, Bahar, R. Iris, Mundy, Joseph, Patterson, William R., Zaslavsky, Alexander. Full Two-Dimensional Markov Chain Analysis of Thermal Soft Errors in Subthreshold Nanoscale CMOS Devices IEEE Transactions on Device and Materials Reliability. 2011; 11 (1) : 50-59 . full text
- Ferri, Cesare, Papagiannopoulou, Dimitra, Bahar, R. Iris, Calimera, Andrea. NBTI-aware data allocation strategies for scratchpad memory based embedded systems 2011 12th Latin American Test Workshop (LATW). 2011 . full text
- Ferri, Cesare, Marongiu, Andrea, Lipton, Benjamin, Bahar, R. Iris, Moreshet, Tali, Benini, Luca, Herlihy, Maurice. SoC-TM Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '11. 2011 . full text
- Tadesse, Desta, Bahar, R. Iris, Grodstein, Joel. Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems Journal of Electronic Testing. 2011; 27 (2) : 123-136 . full text
- Alves, Nuno, Buben, Alison, Nepal, Kundan, Dworak, Jennifer, Bahar, R. Iris. A Cost Effective Approach for Online Error Detection Using Invariant Relationships IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.. 2010; 29 (5) : 788-801 . full text
- Calimera, A., Bahar, R.I., Macii, E., Poncino, M. Dual- assignment policies in ITD-aware synthesis Microelectronics Journal. 2010; 41 (9) : 547-553 . full text
- Ferri, Cesare, Wood, Samantha, Moreshet, Tali, Iris Bahar, R., Herlihy, Maurice. Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems Journal of Parallel and Distributed Computing. 2010; 70 (10) : 1042-1052 . full text
- Ferri, Cesare, Wood, Samantha, Moreshet, Tali, Bahar, Iris, Herlihy, Maurice. Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems Automata, Languages and Programming. 2010 : 50-65 . full text
- Alves, Nuno, Nepal, Kundan, Dworak, Jennifer, Bahar, R. Iris. Improving the testability and reliability of sequential circuits with invariant logic Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10. 2010 . full text
- Jannaty, Pooya, Sabou, Florian C., Bahar, R. Iris, Mundy, Joseph, Patterson, William R., Zaslavsky, Alexander. Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10. 2010 . full text
- Calimera, Andrea, Bahar, R. Iris, Macii, Enrico, Poncino, Massimo. Temperature-Insensitive Dual-Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence IEEE Trans. VLSI Syst.. 2010; 18 (11) : 1608-1620 . full text
- Jannaty, Pooya, Sabou, Florian C., Gadlage, Matthew, Bahar, R. Iris, Mundy, Joseph, Patterson, William, Reed, Robert A., Weller, Robert A., Schrimpf, Ronald D., Zaslavsky, Alexander. Two-Dimensional Markov Chain Analysis of Radiation-Induced Soft Errors in Subthreshold Nanoscale CMOS Devices IEEE Trans. Nucl. Sci.. 2010 . full text
- Tadesse, D., Grodstein, J., Bahar, R. I. AutoRex: An automated post-silicon clock tuning tool 2009 International Test Conference. 2009 . full text
- Alves, Nuno, Dworak, Jennifer, Bahar, Iris, Nepal, K. Compacting test vector sets via strategic use of implications Proceedings of the 2009 International Conference on Computer-Aided Design - ICCAD '09. 2009 . full text
- Alves, N., Nepal, K., Dworak, J., Bahar, R.I. Detecting errors using multi-cycle invariance information 2009 Design, Automation & Test in Europe Conference & Exhibition. 2009 . full text
- Ferri, Cesare, Bahar, Ruth Iris, Loghi, Mirko, Poncino, Massimo. Energy-optimal synchronization primitives for single-chip multi-processors Proceedings of the 19th ACM Great Lakes symposium on VLSI - GLSVLSI '09. 2009 . full text
- Le, Roto, Reda, Sherief, Bahar, R. Iris. High-performance, cost-effective heterogeneous 3D FPGA architectures Proceedings of the 19th ACM Great Lakes symposium on VLSI - GLSVLSI '09. 2009 . full text
- Bahar, R. Iris. Introduction to special section JETC. 2009; 5 (2) : 1-1 . full text
- Sabou, F.C., Kazazis, D., Bahar, R.I., Mundy, J., Patterson, W.R., Zaslavsky, A. Markov Chain Analysis of Thermally Induced Soft Errors in Subthreshold Nanoscale CMOS Circuits IEEE Transactions on Device and Materials Reliability. 2009; 9 (3) : 494-504 . full text
- Reda, Sherief, Si, Aung, Bahar, R. Iris. Reducing the leakage and timing variability of 2D ICcs using 3D ICs Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design - ISLPED '09. 2009 . full text
- Ferri, Cesare, Viescas, Amber, Moreshet, Tali, Bahar, R. Iris, Herlihy, Maurice. Energy efficient synchronization techniques for embedded architectures Proceedings of the 18th ACM Great Lakes symposium on VLSI - GLSVLSI '08. 2008 . full text
- Calimera, A., Bahar, R. I., Macii, E., Poncino, M. Ensuring temperature-insensitivity of dual-Vt designs through ITD-aware synthesis 2008 14th International Workshop on Thermal Inveatigation of ICs and Systems. 2008 . full text
- Tadesse, Desta, Bahar, Iris, Grodstein, Joel. Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation 26th IEEE VLSI Test Symposium (vts 2008). 2008 . full text
- Ferri, Cesare, Reda, Sherief, Bahar, R. Iris. Parametric yield management for 3D ICs JETC. 2008; 4 (4) : 1-22 . full text
- Calimera, Andrea, Bahar, R. Iris, Macii, Enrico, Poncino, Massimo. Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits Proceeding of the thirteenth international symposium on Low power electronics and design - ISLPED '08. 2008 . full text
- Calimera, Andrea, Macii, Enrico, Poncino, Massimo, Bahar, R. Iris. Temperature-insensitive synthesis using multi-vt libraries Proceedings of the 18th ACM Great Lakes symposium on VLSI - GLSVLSI '08. 2008 . full text
- Calimera, A., Duraisami, K., Sathanur, A., Sithambaram, P., Bahar, R. I., Macii, A., Macii, E., Poncino, M. Thermal-Aware Design Techniques for Nanometer CMOS Circuits Journal of Low Power Electronics. 2008; 4 (3) : 374-384 . full text
- Nepal, K., Alves, N., Dworak, J., Bahar, R.I. Using Implications for Online Error Detection 2008 IEEE International Test Conference. 2008 . full text
- Ferri, Cesare, Moreshet, Tali, Bahar, R. Iris, Benini, Luca, Herlihy, Maurice. A hardware/software framework for supporting transactional memory in a MPSoC environment ACM SIGARCH Computer Architecture News. 2007; 35 (1) : 47 . full text
- Tadesse, D., Sheffield, D., Lenge, E., Bahar, R.I., Grodstein, J. Accurate Timing Analysis using SAT and Pattern-Dependent Delay Models 2007 Design, Automation & Test in Europe Conference & Exhibition. 2007 . full text
- Bahar, R.I., Lau, C., Hammerstrom, D., Marculescu, D., Harlow, J., Orailoglu, A., Joyner, W.H., Pedram, M. Architectures for silicon nanoelectronics and beyond Computer. 2007; 40 (1) : 25-33 . full text
- Nepal, K., Bahar, R. I., Mundy, J., Patterson, W. R., Zaslavsky, A. Designing Nanoscale Logic Circuits Based on Markov Random Fields Journal of Electronic Testing. 2007; 23 (2-3) : 255-266 . full text
- Ferri, Cesare, Sherief Reda, None, R. Iris Bahar, None. Strategies for improving the parametric yield and profits of 3D ICs 2007 IEEE/ACM International Conference on Computer-Aided Design. 2007 . full text
- Nepal, K., Bahar, R. I., Mundy, J., Patterson, W. R., Zaslavsky, A. Techniques for Designing Noise-Tolerant Multi-Level Combinational Circuits 2007 Design, Automation & Test in Europe Conference & Exhibition. 2007 . full text
- Li, H., Mundy, J., Patterson, W., Kazazis, D., Zaslavsky, A., Bahar, R. I. Thermally-induced soft errors in nanoscale CMOS circuits 2007 IEEE International Symposium on Nanoscale Architectures. 2007 . full text
- Stojanovic, V., Iris Bahar, R., Dworak, J., Weiss, R. A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors 2006 43rd ACM/IEEE Design Automation Conference. 2006 . full text
- Nepal, K., Bahar, R.I., Mundy, J., Patterson, W.R., Zaslavsky, A. Designing MRF based Error Correcting Circuits for Memory Elements Proceedings of the Design Automation & Test in Europe Conference. 2006 . full text
- Moreshet, Tali, Bahar, R. Iris, Herlihy, Maurice. Energy implications of multiprocessor synchronization Proceedings of the eighteenth annual ACM symposium on Parallelism in algorithms and architectures - SPAA '06. 2006 . full text
- Nepal, K., Bahar, R.I., Mundy, J., Patterson, W.R., Zaslavsky, A. MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits IEEE Micro. 2006; 26 (5) : 19-27 . full text
- Nepal, K., Bahar, R. I., Mundy, J., Patterson, W. R., Zaslavsky, A. Optimizing noise-immune nanoscale circuits using principles of Markov random fields Proceedings of the 16th ACM Great Lakes symposium on VLSI - GLSVLSI '06. 2006 . full text
- Hui-Yuan Song, None, Nepal, K., Bahar, R.I., Grodstein, J. Timing analysis for full-custom circuits using symbolic DC formulations IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.. 2006; 25 (9) : 1815-1830 . full text
- Bahar, R. Iris. Trends and Future Directions in Nano Structure Based Computing and Fabrication 2006 International Conference on Computer Design. 2006 . full text
- Nepal, K., Bahar, R.I., Mundy, J., Patterson, W.R., Zaslavsky, A. Designing logic circuits for probabilistic computation in the presence of noise Proceedings. 42nd Design Automation Conference, 2005.. 2005 . full text
- Moreshet, Tali, Bahar, R. Iris, Herlihy, Maurice. Energy reduction in multiprocessor systems using transactional memory Proceedings of the 2005 international symposium on Low power electronics and design - ISLPED '05. 2005 . full text
- Bahar, R.I., Hui-Yuan Song, None, Nepal, K., Grodstein, J. Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.. 2005; 24 (4) : 502-515 . full text
- Bai, Yu, Bahar, R. Iris. A low-power in-order/out-of-order issue queue ACM Trans. Archit. Code Optim.. 2004; 1 (2) : 152-179 . full text
- Moreshet, T., Bahar, R.I. Effects of speculation on performance and issue queue design IEEE Trans. VLSI Syst.. 2004; 12 (10) : 1123-1126 . full text
- Mehta, N., Singer, B., Bahar, R.I., Leuchtenburg, M., Weiss, R. Fetch halting on critical load misses IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings.. 2004 . full text
- Nepal, Kundan, Song, Hui-Yuan, Bahar, R. Iris, Grodstein, Joel. RESTA Proceedins of the 14th ACM Great Lakes symposium on VLSI - GLSVLSI '04. 2004 . full text
- Yu Bai, None, Bahar, R.I. Reducing issue queue power for multimedia applications using a feedback control algorithm IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings.. 2004 . full text
- Yu Bai, None, Bahar, R.I. A dynamically reconfigurable mixed in-order/out-of-order issue queue for power-aware microprocessors IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.. 2003 . full text
- Moreshet, Tali, Bahar, R. Iris. Power-aware issue queue design for speculative instructions Proceedings of the 40th conference on Design automation - DAC '03. 2003 . full text
- Song, H.-Y., Bohidar, S., Bahar, R.I., Grodstein, J. Symbolic failure analysis of custom circuits due to excessive leakage current Proceedings 21st International Conference on Computer Design. 2003 . full text
- Bahar, R. Iris, Manne, Srilatha. Power and energy reduction via pipeline balancing Proceedings of the 28th annual international symposium on Computer architecture - ISCA '01. 2001 . full text
- Bahar, R. Iris, Lampe, Ernest T., Macii, Enrico. Power optimization of technology-dependent circuits based on symbolic computation of logic implications ACM Trans. Des. Autom. Electron. Syst.. 2000; 5 (3) : 267-293 . full text
- Bahar, R.I., Hyunwoo Cho, None, Hachtel, G.D., Macii, E., Somenzi, F. Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.. 1997; 16 (10) : 1101-1115 . full text
- Bahar, R.I., Frohm, E.A., Gaona, C.M., Hachtel, G.D., Macii, E., Pardo, A., Somenzi, F. Algebraic decision diagrams and their applications Proceedings of 1993 International Conference on Computer Aided Design (ICCAD). 1993 . full text
- Badeau, R.W., Bahar, R.I., Bernstein, D., Biro, L.L., Bowhill, W.J., Brown, J.F., Case, M.A., Castelino, R.W., Cooper, E.M., Delaney, M.A., Deverell, D.R., Edmonson, J.H., Ellis, J.J., Fischer, T.C., Fox, T.F., Gowan, M.K., Gronowski, P.E., Herrick, W.V., Jain, A.K., Meyer, J.E., Miner, D.G., Partovi, H., Peng, V., Preston, R.P., Somanathan, C., Stamm, R.L., Thierauf, S.C., Uhler, G.M., Wade, N.D., Wheeler, W.R. A 100-MHz macropipelined VAX microprocessor IEEE J. Solid-State Circuits. 1992; 27 (11) : 1585-1598 . full text